/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright(c) 2021 Huawei Technologies Co., Ltd */

#ifndef HINIC3_PCI_ID_TBL_H
#define HINIC3_PCI_ID_TBL_H

#define HINIC3_VIRTIO_VNEDER_ID			0x1AF4
#ifdef CONFIG_SP_VID_DID
#define PCI_VENDOR_ID_SPNIC			0x1F3F
#define HINIC3_DEV_ID_STANDARD			0x9020
#define HINIC3_DEV_ID_SDI_5_1_PF		0x9032
#define HINIC3_DEV_ID_SDI_5_0_PF		0x9031
#define HINIC3_DEV_ID_DPU_PF			0x9030
#define HINIC3_DEV_ID_SPN120			0x9021
#define HINIC3_DEV_ID_VF			0x9001
#define HINIC3_DEV_ID_VF_HV			0x9002
#define HINIC3_DEV_SDI_5_1_ID_VF		0x9003
#define HINIC3_DEV_SDI_5_1_ID_VF_HV		0x9004
#define HINIC3_DEV_ID_SPU			0xAC00
#define HINIC3_DEV_SDI_5_1_SSDID_VF		0x1000
#define HINIC3_DEV_SDI_V100_SSDID_MASK (3 << 12)
#elif defined(CONFIG_NF_VID_DID)
#define PCI_VENDOR_ID_NF			0x2036
#define NFNIC_DEV_ID_STANDARD			0x1618
#define NFNIC_DEV_ID_SDI_5_1_PF			0x0226
#define NFNIC_DEV_ID_SDI_5_0_PF			0x0225
#define NFNIC_DEV_ID_DPU_PF			0x0224
#define NFNIC_DEV_ID_VF				0x1619
#define NFNIC_DEV_ID_VF_HV			0x379F
#define NFNIC_DEV_SDI_5_1_ID_VF			0x375F
#define NFNIC_DEV_SDI_5_0_ID_VF			0x375F
#define NFNIC_DEV_SDI_5_1_ID_VF_HV		0x379F
#define NFNIC_DEV_ID_SPU			0xAC00
#define NFNIC_DEV_SDI_5_1_SSDID_VF		0x1000
#define NFNIC_DEV_SDI_V100_SSDID_MASK (3 << 12)
#else
#define PCI_VENDOR_ID_HUAWEI			0x19e5
#define HINIC3_DEV_ID_STANDARD			0x0222
#define HINIC3_DEV_ID_SDI_5_1_PF		0x0226
#define HINIC3_DEV_ID_SDI_5_0_PF		0x0225
#define HINIC3_DEV_ID_DPU_PF			0x0224
#define HINIC3_DEV_ID_VF			0x375F
#define HINIC3_DEV_ID_VF_HV			0x379F
#define HINIC3_DEV_SDI_5_1_ID_VF		0x375F
#define HINIC3_DEV_SDI_5_0_ID_VF		0x375F
#define HINIC3_DEV_SDI_5_1_ID_VF_HV		0x379F
#define HINIC3_DEV_ID_SPU			0xAC00
#define HINIC3_DEV_SDI_5_1_SSDID_VF		0x1000
#define HINIC3_DEV_SDI_V100_SSDID_MASK (3 << 12)
#endif

#define NFNIC_DEV_SSID_2X25G_NF         0x0860
#define NFNIC_DEV_SSID_4X25G_NF         0x0861
#define NFNIC_DEV_SSID_2x100G_NF        0x0862
#define NFNIC_DEV_SSID_2x200G_NF        0x0863

#define HINIC3_DEV_SSID_2X10G			0x0035
#define HINIC3_DEV_SSID_2X25G			0x0051
#define HINIC3_DEV_SSID_4X25G			0x0052
#define HINIC3_DEV_SSID_4X25G_BD		0x0252
#define HINIC3_DEV_SSID_4X25G_SMARTNIC		0x0152
#define HINIC3_DEV_SSID_6X25G_VL		0x0356
#define HINIC3_DEV_SSID_2X100G			0x00A1
#define HINIC3_DEV_SSID_2X100G_SMARTNIC 	0x01A1
#define HINIC3_DEV_SSID_2X200G			0x04B1
#define HINIC3_DEV_SSID_2X100G_VF		0x1000
#define HINIC3_DEV_SSID_HPC_4_HOST_NIC		0x005A
#define HINIC3_DEV_SSID_2X200G_VL		0x00B1
#define HINIC3_DEV_SSID_1X100G			0x02A4

#define BIFUR_RESOURCE_PF_SSID			0x05a1

#endif

